Maximum-Likelihood Stereo Correspondence using Field Programmable Gate Arrays

Authors

  • Siraj Sabihuddin
  • W. James MacLean

DOI:

https://doi.org/10.2390/biecoll-icvs2007-59

Keywords:

stereo, dynamic-programming, FPGA, high frame rate, DDC: 004 (Data processing, computer science, computer systems)

Abstract

Estimation of depth within an imaged scene can be formulated as a stereo correspondence problem. Typical software approaches tend to be too slow for real time performance on high frame rate (>= 30fps) stereo acquisition systems. Hardware implementations of these same algorithms allow for parallelization, providing a marked improvement in performance. This paper will explore one such hardware implementation of a maximum-likelihood stereo correspondence algorithm on a Field Programmable Gate Array (FPGA). The proposed ""FastTrack"" hardware implementation is a first stage prototype that demonstrates comparable results to an equivalent software implementation. with the advantage of high-speed (eventually up to 200fps) stereo depth estimation.

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Published

2007-12-31

Issue

Section

The 5th International Conference on Computer Vision Systems