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Maximum-Likelihood Stereo Correspondence using Field Programmable Gate Arrays

Sabihuddin, Siraj ; MacLean, W. James

The 5th International Conference on Computer Vision Systems, 2007
Bielefeld, 21. - 24. März 2007

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Abstract:
Estimation of depth within an imaged scene can be formulated as a stereo correspondence problem. Typical software approaches tend to be too slow for real time performance on high frame rate (>= 30fps) stereo acquisition systems. Hardware implementations of these same algorithms allow for parallelization, providing a marked improvement in performance. This paper will explore one such hardware implementation of a maximum-likelihood stereo correspondence algorithm on a Field Programmable Gate Array (FPGA). The proposed ""FastTrack"" hardware implementation is a first stage prototype that demonstrates comparable results to an equivalent software implementation. with the advantage of high-speed (eventually up to 200fps) stereo depth estimation.


Keywords: stereo, dynamic-programming, FPGA, high frame rate
Institution: Faculty of Technology, Research Groups in Informatics
DDC classification: Data processing, computer science, computer systems

Suggested Citation:
Sabihuddin, Siraj ; MacLean, W. James  (2007)  Maximum-Likelihood Stereo Correspondence using Field Programmable Gate Arrays. The 5th International Conference on Computer Vision Systems, 2007


URL: http://biecoll.ub.uni-bielefeld.de/volltexte/2007/53



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