Implementation of an Affine-Covariant Feature Detector in Field-Programmable Gate Arrays

Authors

  • Cristina Cabani
  • W. James MacLean

DOI:

https://doi.org/10.2390/biecoll-icvs2007-10

Keywords:

feature detector, interest point detector, field-programmable gate array, smart camera, embedded vision, DDC: 004 (Data processing, computer science, computer systems)

Abstract

This article describes an FPGA-based implementation of the Harris-Affine feature detector introduced by Mikolajczyk and Schmid. The system is implemented on the Transmogrifier-4, a prototyping platform that includes four Altera Stratix S80 FPGAs and NTSC/VGA video interfaces. The system achieves a speed of 90-9000 times the speed of an equivalent software implementation, allowing it to process standard video (640 x 480 pixels) at 30 frames per second.

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Published

2007-12-31

Issue

The 5th International Conference on Computer Vision Systems (ICVS)

Section

The 5th International Conference on Computer Vision Systems